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Automatic Generation of Design Constraints in Verifying High Performance Embedded Dynamic Circuits Disclosure Number: IPCOM000009237D
Original Publication Date: 2002-Aug-13
Included in the Prior Art Database: 2002-Aug-13

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Jayanta Bhadra Narayanan Krishnamurthy


Design constraints are artifacts that model an environment of a design under verification by restricting input stimuli to plausible valuations. Judicious usage of design constraints can be effective in eliminating false verification results. Given a particular verification problem, however, it is a difficult proposition to write down all the necessary constraints. We present a technique for automatic generation of design constraints from simple user-provided information about potential design environments. Our method generates a set of design constraints representing varying degrees of assumptions about potential environments of a dynamic circuit. We also present experimental results on verification of custom designed embedded dynamic circuits taken from the Motorola MPC7455 microprocessor that is compatible with the PowerPC instruction set architecture.