TESTING SIGNALS DERIVED FROM AN EXTERNAL CLOCK SIGNAL
Original Publication Date: 1999-Jun-01
Included in the Prior Art Database: 2002-Aug-14
This proposal relates to testing of circuits like memory controllers. As illustrated in Figure 1, the circuit often receives an external clock EXT (50% duty cycle). Internally, the circuit derives an internal clock INT (also 50% duty cycle) at twice the rate of EXT, and N=4 or more clock ticks TICK-n having phase- shifted on-times (e.g., 257% duty cycle). INT and TICK-n can be combined as defined by the user.