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Disclosed is a method for determining optimal die-bump and package dimensions to enable robust power delivery. Benefits include improved design environment.
English (United States)
This text was extracted from a Microsoft Word document.
This is the abbreviated version, containing approximately
60% of the total text.
Method for determining optimal die-bump and package
dimensions to enable robust power delivery
Disclosed is a method
for determining optimal die-bump and package dimensions to enable robust power
delivery. Benefits include improved design environment.
� � � � � � � � Nonuniformity
of via placement occurs in the 1F-layer trace direction when vias are dropped
from the 2F layer to the 1F layer. As a result, design complications occur such
as a less robust power bussing design and greater design time.
� � � � � Conventionally, the nonuniformity is solved bymanual adjustment of individual 2F-1F vias
on a case-by-case basis. Solutions include extended design time and poor
flexibility in the case of new design rules, shrinks or other design changes. This manual adjustment is difficult to
� � � � � The disclosed method determines the
optimal die-bump and package dimensions, including:
Optimum power bussing trace width on the 1F layer
Optimum bump pitch in the x-direction
Pin through hole (PTH) pitch in the x-direction
� � � � � The method provides flexibility in the
y-direction to enable minimum loop inductance and reduce design time. With low
loop inductance, the package has a better path to the decoupling capacitors so
that less power-supply noise occurs. As a result, the processor is able to
achieve a higher maximum frequency.