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SOMOS Formation by Lateral Oxidation Disclosure Number: IPCOM000009371D
Original Publication Date: 2002-Aug-20
Included in the Prior Art Database: 2002-Aug-20

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Christopher C. Hobbs


SONOS (poly-Si/SiO2/Si3N4/SiO2/Si-substrate) gate stack structures have been used to fabricate memory devices. The device is programmed by applying a voltage to the gate to inject charge into the Si3N4 that results in a threshold voltage shift. When the voltage is removed, the charge remains in the Si3N4 layer because it is contained in traps between the SiO2 layers. The device is erased by applying a reverse bias voltage to remove the trapped charged from the Si3N4. Typically, the SiO2 adjacent to the Poly-Si gate is thicker than the SiO2 adjacent to the Si-substrate so that charge injection occurs through the bottom SiO2 layer. One important characteristic for a SONOS memory device is that the nitride layer contains traps to hold the injected charge. Analysis of insulators such as zirconium dioxide (ZrO2) and hafnium dioxide (HfO2) has found that metal oxide materials also contain traps that are capable of holding injected charge. As a result of this electrical characteristic, the nitride layer can be replaced with a metal oxide to form a SOMOS (poly-Si/SiO2/metal-oxide/SiO2/Si-substrate) gate stack memory device. On a chip, it is desirable to have memory devices with long charge retention times so that the programmed threshold voltage does not significantly drift with time. This means that the SiO2 layers on either side of the metal oxide must be good insulators. In a conventional SONOS integration process, the upper SiO2 layer is typically formed with a deposition process. Unfortunately, the insulating properties of deposited SiO2 films are typically poorer than a thermally grown SiO2 layer. One advantage in replacing the Si3N4 with a metal oxide is that a memory device can be formed wherein the upper SiO2 layer is thermally grown after the gate electrode is in place. This integration proposes using the lateral oxidation mechanism (Hobbs et al., 2001 IEDM Technical Digest, p30.1.1-4) to form a SOMOS memory device. It consists of (a) forming a polySi (or SiGe) gate on top of a metal oxide gate dielectric and (b) performing an oxidation that will grow interfacial oxide layers above and below the metal oxide gate dielectric.