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Binary Mask Layout Technique for Improved Contact Hole Process Latitude

IP.com Disclosure Number: IPCOM000009372D
Original Publication Date: 2002-Aug-20
Included in the Prior Art Database: 2002-Aug-20

Publishing Venue

Motorola

Related People

Authors:
Kirk J. Strozewski

Abstract

The long-term trend in the semiconductor industry has been, and is expected to continue to be, needing to pattern ever-smaller features on ever-tighter pitches. In general, these smaller features and pitches pattern well over a smaller and smaller range of process input parameters. In particular, the “depth of focus” is shrinking rapidly, making defect-free patterning increasingly difficult. Methods that increase the range of parameters (or latitude) over which patterning is successful will result in fewer wafer-level defects leading to higher yield and lower die cost. Various techniques have been proposed to increase process latitude with some of them in use. Two of several general groups involve changes to the reticle and changes to the reticle illumination system. Examples of reticle changes include the addition of small subresolution features and the use of partially transmissive masks. Examples of reticle illumination techniques include optimization of partial coherence and the use of so-called “off-axis” techniques. Nevertheless, these latitude enhancement techniques often have limitations of their own. For example, using a partially transmissive mask can result in substantial benefits for small features on large pitches but tends to produce little benefit at tighter pitches, and in addition is more expensive mask. Off-axis techniques can result in substantial benefit for small features on small pitches but does little for small features on larger pitches, which in general must be patterned well also. As one can also expect, the lowest cost process is also desired.