Publishing Venue
The IP.com Prior Art Database
Abstract
Disclosed is a method that improves Dual Data Rate SDRAM (DDR) read operations with a process that detects data arrival in relation to the MCH memory core clock. Benefits include cost reductions and simplified read operations.
DQS Timing Calibration Based on
High-Speed Capture of a Deterministic Data Pattern
Disclosed is a method that improves Dual Data Rate SDRAM (DDR) read operations with a process that
detects data arrival in relation to the MCH memory core clock. Benefits include
cost reductions and simplified read operations.
Background
Currently,
for DDR read operations, the Data
Strobe (DQS) signal is calibrated to provide adequate setup and hold
time for incoming read data. However, due to system uncertainty the data arrival
time of the DQS strobes vary. In addition, the DQS signal is Stub Series Terminated Logic (SSTL),
which can cause noise associated with the DQS signal to inadvertently change
internal pointers; this requires that the Memory
Controller Hub (MCH) input buffer is only turned during DQS reads.
General Description
The disclosed method uses the following procedure to detect
data arrivals in relation to the MCH memory core clock (see Figures 1 and 2):
- Memory
locations are written with either 0s or 1s.
- Back to Back reads are to memory
locations written with 0s (Rd-0), followed by reads to memory
locations written with 1s (Rd-1).
- The
DQS input buffer is enabled during the data arrival.
- A
shift register samples incoming DQ data on both the rising and falling
edge of a high-speed internal clock.
- A data
pattern change from Rd-0 to Rd-1 causes the capturing register to detect
a 0 to 1 shift.
- The
capture signature is fed to a configuration register, and programmed when
the DQS input...