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METHOD FOR TOLERATING SCHEDULING LATENCY IN HIGH SPEED MODEMS IMPLEMENTED ON HOST PROCESSORS

IP.com Disclosure Number: IPCOM000009408D
Original Publication Date: 1999-Sep-01
Included in the Prior Art Database: 2002-Aug-21
Document File: 6 page(s) / 255K

Publishing Venue

Motorola

Related People

Authors:
Jian Yang

Abstract

With host processors in personal computers becoming more and more powerful, it becomes fea- sible to implement high speed modems such as ADSL modems in software. However, computation complexity or mips is not the only challenge for a successful implementation of high speed modems. The DSP functions for the high speed modems require real-time execution. However, the host processor may be running many other tasks concur- rently such that its operating system may not be able to guarantee the timely execution of the real-time DSP functions, i.e. there is large response delay. If not being dealt properly, the large response delay can cause transmit buffer underflow and/or receive buffer overflow.