TIMER HANDOVER WITH ZERO LATENCY IN A MULTIPROCESSOR SYSTEM
Original Publication Date: 1999-Sep-01
Included in the Prior Art Database: 2002-Aug-22
Switching PLL off/on to attain a low power mode causes a timer halt in the DSP processor. This time lapse desynchronizes the radio with the system and causes an out of sync condition to occur. Recovering from this case would be as difficult as reacquiring sync with the system similar to a power up state sequence. Since the current consumption in regular wait mode is too high, it is necessary to find a solution to the timer halt during all PLL state tran- sitions.