STANDARD CELL LIBRARY DESIGNED FOR IDDQ TESTING
Original Publication Date: 1999-Sep-01
Included in the Prior Art Database: 2002-Aug-28
A design methodology for logic is described which provides for the easy application of a voltage across the gate-drain, gate-source, and gate-bulk of all transistors in the circuit. This can be accom- plished in only two test vectors. If the static Idd cur- rent is measured during these two test vectors, the integrity of all gate oxides can be verified. This methodology provides a practical way to do ideal static Idd testing. The penalty for this added testabil- ity is small.