Browse Prior Art Database

ADAPTIVE LOOP BANDWIDTH CONTROL ARCHITECTURE FOR SYNTHESIZER APPLICATIONS

IP.com Disclosure Number: IPCOM000009523D
Original Publication Date: 1999-Sep-01
Included in the Prior Art Database: 2002-Aug-29

Publishing Venue

Motorola

Related People

Authors:
Richard M. Dougherty

Abstract

With the present emergence of far-reaching communication systems, the need for improved syn- thesizer performance has received renewed focus. Conjointly, synthesizers operating over several frequency decades and providing excellent phase noise, quick settling time, fine frequency step size and low spurious performance has gained new prominence. The problem normally encountered regarding these requirements is that circuit condi- tions for fast settling time, fine frequency step size and low spurious performance are diametrically opposed. In order to address this, synthesizer designs have evolved into multi-loop designs employing adaptive architectures.