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MULTIPLE TEST ACCESS PORTS FOR ON-MODULE TESTING OF A SINGLE INTEGRATED CIRCUIT

IP.com Disclosure Number: IPCOM000009545D
Original Publication Date: 1999-Sep-01
Included in the Prior Art Database: 2002-Sep-02

Publishing Venue

Motorola

Related People

Authors:
Moshe Solar Avraham Ganor Yoram Yeivin

Abstract

The Joint Test Action Group (JTAG) standard IEEE 1149.1 "Test Access Port and Boundary-Scan Architecture" was developed with the intention to have only a single test access port (TAP) for each integrated circuit (IC). However, it became very common to manufacture KS with multiple TAPS. ICs can be designed to use multiple cores which contain their own TAPS so that a single IC can con- tain core multiple TAPS.