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Disclosed is a method for a double data rate (DDR) cycles launch throttling scheme that prevents receive (RCV) first-in, first-out (FIFO) buffer overflows. Benefits include improved performance.
English (United States)
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65% of the total text.
Method for a DDR cycles launch throttling scheme that prevents receive
FIFO buffer overflows
Disclosed is a method for a double data rate
(DDR) cycles launch throttling scheme that prevents receive (RCV) first-in,
first-out (FIFO) buffer overflows. Benefits include improved performance.
� � � � � A
data queue (DQ) buffer has a receive (RCV) FIFO that latches DRAM data
corresponding to each rising and falling data queuing system (DQS) signal edge.
The depth of this RCV FIFO is determined using worst/best case analysis of data
arrival with respect to the command launch in different DRAM system
configurations. The analysis involves simulation data that could be very
different from the actual system data. This situation could result in an
overflow condition of the RCV FIFO, corrupting data for back-to-back read data
� � � � � The
memory controller receives read commands from master agents to be launched on
the DRAM bus. Then, the controller issues an nput
signal to the issuing agent, signifying valid 32‑byte data to be sampled in the
next clock. That is, after the nput,
32-bytes of data from the RCV FIFO has been drained.
� � � � � The
disclosed method is a limiting (throttling) technique to prevent the overflow
of the RCV FIFO in a DQ buffer. A counter is maintained to keep track of the
outstanding 32-byte read commands (see Figure 1). This counter is incremented
when a 32-byle read command is launched on the DRAM bus. The same counter is