TWO'S COMPLEMENT ADDER ARCHITECTURE THAT MINIMIZES PROPAGATION DELAY
Publication Date: 2002-Sep-19
The IP.com Prior Art Database
Wen Shu: AUTHOR [+1]
Allows the hardware to perform a 2's complement number in a faster fashion.It can be any number of binary bits.
TITLE: "TWO'S COMPLEMENT ADDER ARCHITECTURE THAT MINIMIZES PROPAGATION DELAY"
INVENTORS: Wen Shu (Opuswave Networks, Inc.)
FILE NO. 99E9503US
1. Please give a brief descriptive title to your invention:
Two's compliment adder architecture that minimizes propagation delay.
2. Briefly describe the problem (or problems) which your invention solves:
Allows the hardware to perform a 2's complement number in a faster fashion.
It can be any number of binary bits.
3. Describe the prior approaches you know of which add or attempt to solve the same
problem(s) most nearly similar to the problem� your inwnention solves:
Previous version of 2's complement has had more logic levels. The data is inverted first, and then add a 1 to the LSB bit. It introduces more delay to the data interchange. This new approach eliminates the data invert logic level. Data to be interchanged performs the invert and add function in one logic level.
4. PIease describe the physical structure of your invention in detail. If your invention is a computer program, describe the compiler platform for which it wvas written and an appropriale block diagram or flow chart. Existing drawings can be used instead of a wrilten description.
From the 2's complement chart belovv, it can be observed that from left to right, all '0' bits plus the first .
I' bit are remain unchanged (in black) From this first '1' bit, invert the rest of the up bits (in red).