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Browse Prior Art Database

HARDWARE RETURN STACK PERFORMANCE OPTIMIZATION

IP.com Disclosure Number: IPCOM000009920D
Original Publication Date: 2000-May-01
Included in the Prior Art Database: 2002-Sep-27
Document File: 3 page(s) / 156K

Publishing Venue

Motorola

Related People

Authors:
Joe Circello David Schimke Jeff Freeman

Abstract

All architectures of the ColdFire family of 32bit embedded microprocessors implement a decoupled pipeline strategy, where the operation of the Instruction Fetch Pipeline (IFF) is decoupled from the Operand Execution Pipeline (OEP) through the use of a FlFO instruction buffer. This mechanism allows the IFP to prefetch instructions in advance of their actual use by the operand pipeline. In the Version 3 and Version 4 Instruction Fetch Pipelines, one stage is dedicated to performing time-critical decode functions on the prefetched instructions.