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Filtering out Repetitive Errors During Simulation-Based Verification of an IC Layout

IP.com Disclosure Number: IPCOM000009959D
Publication Date: 2002-Oct-01
Document File: 6 page(s) / 103K

Publishing Venue

The IP.com Prior Art Database


An approach to better handling repettive errors reported during simulation-based verification of an integrated circuit layout is described. This reduces the manual review, or inspection, time spent on going through the output of the verification.