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Method to accelerate SAT-based formal verification of RTL assertions in industrial scale VLSI designs

IP.com Disclosure Number: IPCOM000010051D
Publication Date: 2002-Oct-16

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to accelerate satisfiability solver (SAT) based formal verification of resister transistor logic (RTL) assertions in industrial very large scale integration (VLSI) designs. Benefits include faster verification and verification of more properties.