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Fast Divide Algorithm with minimum Expression of the redundant Partial Remainder

IP.com Disclosure Number: IPCOM000010389D
Original Publication Date: 2002-Nov-22
Included in the Prior Art Database: 2002-Nov-22

Publishing Venue

IBM

Abstract

A fast SRT Divide Algorithm with minimum expression of redundant partial remainder is shown. State of the art designs use the carry part in the same width as the sum part for the redundant expression of the partial remainder. The carry part can be reduced without having disadvantages for performance and cycle time. The advantage is a reduced area and power consumption. The implemented example saves 82 latches with a total width of 116 bits for the SRT divide logic.