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A recursive „at-speed“ Built-In Self-Repair (BISR) method for the allocation of redundant rows and columns in an embedded-RAM

IP.com Disclosure Number: IPCOM000010425D
Original Publication Date: 2002-Dec-25
Included in the Prior Art Database: 2002-Dec-25

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Redundant columns and/or rows are commonly employed for the repair of embedded-DRAMs (Dynamic Random Access Memories)/ SRAMs (Static Random Access Memories) in order to improve final chip yield. Once that the faulty locations of the memory array have been found through a memory test, the problem to determine the optimal allocation of the redundant resources, in case that both spare rows and spare columns are present, is NP-hard, meaning that no algorithm with reasonable complexity can be developed to give a general solution to this problem. Therefore a heuristic solution is necessary. Moreover, when the memory test & repair has to be performed on-chip, if the full memory failure bitmap had to be stored, an amount of memory equivalent to the memory under test would be necessary to keep this information. On the other hand, if the full memory failure bitmap is not known in advance, choosing whether allocating either a spare column or a spare row might lead to a non-optimal use of the redundant resources, being the rest of the memory still untested. Commonly used techniques are based on column-first or row-first approaches, thus reducing the problem computational complexity, but at the expense of a decrease of the possible memory failures that can be repaired. Therefore the solution reached by these methods is sub-optimal, because a possibility exists that the memory part be rejected, even though it could be repaired with an optimized redundancy allocation. Other solutions focus on compressing the faulty bitmaps extracted during BIST, keeping only the meaningful information for the selection of the redundant wordlines/ bitlines and discarding the rest of the bitmap. Depending on the redundancy configuration (n. of spare rows/columns), these methods need significant on-line processing capability during the test, so that the algorithm has to be stopped, affecting the fault coverage; in particular they are not suited for at-speed test, since it looks extremely hard to perform all the calculations needed for the bitmap compression within only one clock cycle. An additional drawback of the proposed methods is that the redundant resources are not tested, so a final test run is necessary on the repaired memory. Hereafter a new method to reach the optimal solution is presented, allowing repairing all the repairable memories with a given number of spare rows and columns. The method is based on an iterative algorithm which minimizes the amount of storage needed, by storing only the failure bitmaps necessary to perform a first choice between one redundant row and one redundant column. The information stored is the raw failure bitmap coming out from the BIST, so that no additional computation is needed during the test phase. The bitmap analysis as well as the choice of the redundant wordline/ bitline to allocate is performed after the end of test with no impact on the test fault coverage. After each choice, the test&repair algorithm is run again in a recursive fashion, until either all the faults are fixed (i.e. the memory has been repaired and the redundant resources, if used, have also been tested), or all the redundant resources have been consumed and still some faults exist (i.e. the memory is not repairable). The overall architecture of the Built-In Self-Repair (BISR) system and the detailed algorithm description are given in the following.