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IP.com Disclosure Number: IPCOM000010439D
Publication Date: 2002-Dec-02
Document File: 8 page(s) / 81K

Publishing Venue

The IP.com Prior Art Database


A structure and method of forming a semiconductor power device having ESD, over-temperature and over-voltage protection schemes and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes. The diodes protect the device by clamping the device’s sustaining voltages to the total avalanche voltage of the diode. Historically, providing ESD protection for high density power MOSFET’s operating in the 8 to 500 volt range and having low on resistance (Rdson) has been difficult. Complicating factors include the use of self aligned implants and contacts as well as the many complicated and expensive process steps required to realize the finished device. Furthermore, complicated interconnections to gate and source are required which add further cost and processing steps. Prior methods primarily utilize non-self aligned power MOSFET technologies which suffer from less than optimal electrical performance and high cost. Therefore, it would be advantageous to provide a structure and method of integrating polysilicon diodes with a power MOSFET device. This will in turn allow for integrating ESD protection, temperature sensing, over-temperature protection and over-voltage protection features. Keywords ESD, MOSFET, POWER DEVICE, SELF-ALIGNED, POLY DIODE, TEMPERATURE SENSING, OVER-VOLTAGE PROTECTION