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Support of an External, User Defined, Co-processor in a Multiprocessor/Network Processor Environment Disclosure Number: IPCOM000010520D
Original Publication Date: 2002-Dec-10
Included in the Prior Art Database: 2002-Dec-10
Document File: 2 page(s) / 44K

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This article describes a small change to a network processor that enables the use of externally connected co-processors via the "Co-Processor Response Bus". A coprocessor manager is built into the network processor to manage this bus, allowing a co-processor to be added to the system external to the network processor. This external co-processor can be accessed by all threads within the network processor by using the co-processor manager.

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  Support of an External, User Defined, Co-processor in a Multiprocessor/Network Processor Environment

In a network processor environment, co-processors, implemented in hardware, are used to perform well-known functions very quickly while reducing the number of software instructions significantly. The IBM PowerNP Network Processors contain multiple data plane processors with several hardware co-processors all in one VLSI module. These Network Processors (NP) have long development cycles. Thus, any co-processor implemented in the same module as the data plane processors must be developed, designed, and implemented months before the customer receives the network processor module. During any product development, it is impossible to know all of the potential customer requirements months before release. And, each customer may have a different application which requires a different hardware co-processor. Thus, it is desirable to be able to add co-processors to a multiprocessor environment external to the VLSI module. This allows customers to develop co-processors for their specific applications. And, this enables the development of additional hardware co-processors to customers without manufacturing an entirely new version of the network processor.

     A "Co-Processor Response Bus" (CRB) is added to the pins of the NP. The CRB is an input only bus. This bus allows an external co-processor to return data (20 bits user defined) to a particular processor/thread within the multiprocessor environment. Which processor/thread receives the data is determined by a processor/thread number which is written to the network processor by an external co-processor when the data is written.

     The external co-processor must receive data, be initialized, or at least be started by (an) output signal(s) from the NP. Typically this is accomplished by using the external Look-Up SRAM interface on the NP. When an external co-processor is implemented, the external Look-Up SRAM is replaced by the external co-processor. The external co-processor also connects to the CRB. The external co-processor can receive data or commands via write operations on the external SRAM interface. The external co-processor can provide read data via read operations on the external SRAM interface if the 20 bits of user defined result data via the CRB is not enough.

     The Co-Processor Manager interfaces to each thread of each data plane processor independently via a thread-specific coprocessor interface. The Co-Processor Manager is also connected to the input only Co-Processor Response Bus (CRB).

     The Co-Processor Manager supports one read-only 20 bit scalar register (CrbResults) per coprocessor interface. The external co-processor supported by the Co-Processor Manager can have many more commands, registers, arrays, etc. accessible via software. The Co-Processor Manager allows external co-processors to be added to the NP. The external co-processors are controlled and accessed via software (picocode)...