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Effective Floating Point Code Generation with SSE/SSE2 Instructions for Intel Architecture

IP.com Disclosure Number: IPCOM000010791D
Original Publication Date: 2003-Jan-22
Included in the Prior Art Database: 2003-Jan-22

Publishing Venue

IBM

Abstract

This article describes a technique to generate code for efficient and fast floating point operation for Intel IA-32 architecture with SSE/SSE2 instructions available.