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XOR-Network for LBIST and LFSR-Coding Disclosure Number: IPCOM000010840D
Original Publication Date: 2003-Jan-24
Included in the Prior Art Database: 2003-Jan-24

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This paper concerns VLSI manufacturing test in scan chain design. It describes a hardware and method for 1) generating pseudo random patterns in parallel for Built-in Selftest (LBIST) and 2) for expanding test vectors for compressed stored pattern testing (LFSR-Coding). The novel XOR-network supplies a multiple of scan chains required for LBIST. It reduces the noise and enables more efficient LFSR-Coding. The advantages are demonstrated by simulation runs in comparison to conventional hardware.