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Taking care of Spare cells for easy FIB Disclosure Number: IPCOM000010896D
Original Publication Date: 2003-Feb-25
Included in the Prior Art Database: 2003-Feb-25

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Usually after the first silicon is available there will be some metal redesign needed and this is easily done with the help of spare cells inserted along with the functional logic. The following problem is to be solved by the invention: Since the inputs cannot be left floating they are tied to VDD or VSS and with 5 layer metal routing, the accessibility to the spare gate inputs is not there as the VDD/VSS connections are in Metal1 or Metal2. Making cuts into the bottom layers is not that easy due to the dense routing. With the approach mentioned below, the cuts can be made at the toplevel itself and of course the ease of synthesis and layout. Up to now, the problem has been solved by creating the spare cells as a macro or with some manual intervention of the inputs which have been tied to VDD or VSS is brought to the last metal layer. But this is not always done as the synthesis approach is typically top-down. The invention: For smaller chips even if the spare cells are placed in the toplevel there is no major problem for designs up to 0.35μ design. But for 0.18μ design, the routing delay is also quite significant that the spare cells have to be more local than global. Instead of tying the inputs to the VDD or VSS, all the inputs are tied together and taken to the toplevel of the modul being laid out as a macro. Since this is a separate pin, it is possible to specify to the layout, that this particular signal will be treated with care and routed as the last metal layer for that module. The advantages of this approach are: 1. Synthesis can be done top-down, without special care for the spare cells. 2. On a larger module, we could flatten the layout without giving due thought to the location of spare cells etc. 3. Layout scipts will automatically ensure that the inputs to the cells are available on the top metal layer. 4. For the metal redesign it is much easier to have the same hierarchical netlist, as the changes are within the module. In this way, it is possible to do an easy FIB, as the inputs to all the spare gates are available on the top metal layer. On the chip level these pins can be tied to VDD or VSS, but the modules laid out as hard macros in the hierarchical netlist should have a separate pin and should not be named as any VDD or VSS, so that the layout tool is not confused.