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Digital spike filter with scannable nodes

IP.com Disclosure Number: IPCOM000010897D
Original Publication Date: 2003-Feb-25
Included in the Prior Art Database: 2003-Feb-25
Document File: 3 page(s) / 115K

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Abstract

In digital designs filters have to be implemented to clean up incoming external signals like interrupts from spikes. The filter of this invention eliminates high as well as low signal pulses, which are shorter than the group delay of the delay line used. Innovation of this design Filtering as described above has been done so far by connecting two complete spike filters in series. This results in redundant logic especially, if the delay line is considerably long. Another approach already uses the one line, but the output signal is generated by multiplexers using a combinatorical feedback loop, which is a problem for static timing analysis in general. Additionally, the logic may be modified by the logic optimizer of the synthesis tool, so that direct instantiation of multiplexers is required. These problems can be prevented by using a RS FF which has not to be necessarily a scan FF. The advantages of this approach are:  No redundant logic and reduced area, since only one delay line is used.  No combinatorical feedback loop.  Improved test coverage: only one node is not covered in structural tests like scan.  The functional test of the filter can be reduced to a simple „static signals passing“ test. Although a sequential element is used here, the filter still works completely asynchronous using the set / reset inputs of the RS FF. The data signal experiences no inversion.