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A Layout Technique For Geometric Placement Independence and Improved Matching on Integrated Circuit Leaf Cells Using Circuit Degeneration and Rotational Symmetry Disclosure Number: IPCOM000011194D
Original Publication Date: 2003-Feb-13
Included in the Prior Art Database: 2003-Feb-13
Document File: 4 page(s) / 59K

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This article describes a technique for improving the matching between circuits placed on an integrated circuit. It is well known that the geometric placement of individual circuits affects the matching between these circuits and this places constraints on how circuits are placed at the chip level. This article describes how this constraint can be removed by addressing the problem at the circuit ( or leaf cell ) level through circuit degeneration, thereby providing multiple circuit elements that can then be individually placed in the different geometric orientations which are of concern. Consequently the circuit can be made to be symmetrical for all of the geometric placements of it which are possible at the chip level. This technique has advantages for the application of leaf cells in semi-custom and ASIC ( application specific integrated circuits ) design by removing constraints on how such cells need to be placed.

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  A Layout Technique For Geometric Placement Independence and Improved Matching on Integrated Circuit Leaf Cells Using Circuit Degeneration and Rotational Symmetry

This idea improves matching between circuit blocks placed at different locations on a chip, this problem is well known with various solutions to alleviate this problem having been published. Within the semi-custom or ASIC design flow, this problem is now becoming more relevant as decreasing feature size and increasing analog content ( to realise 'System on a Chip' solutions ) is making circuit matching a design concern within this environment. Previous solutions have really been intended for the semiconductor device or full custom integrated circuit solution where there is more freedom to tackle this problem at the device level by using more complex device structures. In the ASIC level, it is more difficult and expensive to approach this problem in this way, also using special layouts at the device level may not even be compatible with the design system. This disclosure approaches the problem in a different way by using circuit degeneration instead to split circuits up into multiple, identical components with an identical circuit response to the original circuit, the placement of these components can now be made at the leaf cell level in such a way that layout symmetry is preserved across all the valid placement positions of that cell in the ASIC design system. In this way the designer of the ASIC is freed from having to consider matching as part of the leaf cell placement decision, instead the designer of the leaf cell itself is able to control the matching issues exclusively using this technique and since the leaf cell designer is predominantly working at the device level, it is particularly convenient to confine the matching problem to this lowest level of hierarchy in the ASIC design process.

    The core idea is to use circuit degeneration at the leaf cell level on the areas of the circuit that are sensitive to geometric matching, The circuit is degenerated into a number of equal sub-components, the number of sub-components equals the number of degrees of freedom of placement which affect the circuit matching. The technique of rotational symmetry is then used to place each of these sub-components into each of these placement positions. In this way the circuit matching will be preserved as it is placed in the different placement positions at the chip level. This disclosure solves the problem of the placement of a leaf cell affecting matching between instances of the leaf cell at the chip level. This problem was previously handled by placing constraints on the usage of the leaf cell at higher levels of the design.

    It is well known within semiconductor device and integrated circuit design that matching of devices can be important within certain circuits. The traditional techniques that have been used to improve the matching of devices have focused on attaining geometric sym...