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A Layout Technique For Geometric Placement Independence and Improved Matching on Integrated Circuit Leaf Cells Using Circuit Degeneration and Rotational Symmetry Disclosure Number: IPCOM000011194D
Original Publication Date: 2003-Feb-13
Included in the Prior Art Database: 2003-Feb-13

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This article describes a technique for improving the matching between circuits placed on an integrated circuit. It is well known that the geometric placement of individual circuits affects the matching between these circuits and this places constraints on how circuits are placed at the chip level. This article describes how this constraint can be removed by addressing the problem at the circuit ( or leaf cell ) level through circuit degeneration, thereby providing multiple circuit elements that can then be individually placed in the different geometric orientations which are of concern. Consequently the circuit can be made to be symmetrical for all of the geometric placements of it which are possible at the chip level. This technique has advantages for the application of leaf cells in semi-custom and ASIC ( application specific integrated circuits ) design by removing constraints on how such cells need to be placed.