Pipeline control for a low-power microprocessor
Original Publication Date: 2003-Mar-06
Included in the Prior Art Database: 2003-Mar-06
According to the present invention, information about the success (or lack thereof) of executing an instruction in accordance with the teachings described in US Patent 6192466 is used to reduce power dissipation by de-energizing pipeline stages executing instructions which are indicated as having to be re-issued. In one embodiment, this is achieved by clock-gating substantial portions (or all) of a pipeline stage currently executing an instruction being associated with said indicator.