Superscalar microprocessor implementation having merged scalar and multimedia datapath
Original Publication Date: 2003-Mar-06
Included in the Prior Art Database: 2003-Mar-06
According to the present invention, a processor has the ability to issue scalar and SIMD instructions to a datapath. In accordance with this invention, a processor contains an instruction issue stage which detects when a plurality of compatible instructions in the issue queue are ready and can be processed simultaneously within the lanes of a SIMD data path. According to the present invention, the instructions are issued simultaneously, and proceed in the pipeline as a single packet. In one embodiment, the instructions execute the same operation in all lanes. In another embodiment, the instructions are from a set which have common characteristics, such as latency, the number of inputs, and so forth, which make them amenable to simultaneous execution.