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Hardware performance monitor support for profiling translation
miss resolution data structures
English (United States)
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Hardware performance monitor support for profiling translation misses providing address of information used to resolve the miss
On microprocessors with hardware translation (be it page-level or segment-level), the resolution of translation misses requires accessing structures in memory which are usually established initially by software. Identifying translation misses and their resolution structures can be important to performance tuning software.
Most microprocessors include a hardware performance monitor which includes sampling support. The sampling mechanism "freezes" the instruction and data address (if appropriate) of events periodically. This invention is that on translation misses, in addition to the instruction and data address, the performance monitor also stores the address of the translation resolution structure. More specifically, on the translation miss, the instruction and data address of the operation (load, store, or other) is saved. When the tablewalk mechanism finds the translation structure, it too is saved in a register. Software periodically extracts this information and exposes it via performance tools. Note that the translation structure address may be compressed in some way. For example, on PowerPC,* TLB resolutions is by PTEG, which exist on 16-byte boundaries. Thus, right shifting the address by a few bits is still sufficient to uniquely identify the resolution structure.
* Trademark of International Business Machines Corporation