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Digital Reset-Based State Machine Synchronizer Disclosure Number: IPCOM000011621D
Original Publication Date: 2003-Mar-10
Included in the Prior Art Database: 2003-Mar-10

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Hector Ricardo Sucar


State machines are commonly used structures in the design of integrated circuits to implement control and data generation functions. Most state machines are synchronous mechanisms defined to provide a specific sequence of states. Setting and maintaining state machine sequence synchronization is a requirement for correct system operation. This work presents a new method for implementing self-synchronizing state machines with negligible performance impact. The synchronization approach is independent of the actual state machine logic implementation. Hence, optimal performance may be achieved. The synchronization method provides a power-on-reset-type capability to set initial synchronization and constantly verifies sequence correctness through the operation of the device providing synchronization recovery if necessary. Thus, maintaining state machine synchronization. The implementation is fully digital and it could be built using standard IC technologies (CMOS, BiCMOS, Bipolar, etc.).