Browse Prior Art Database

A Tapered Power Grid Design and Optimization Method

IP.com Disclosure Number: IPCOM000011626D
Original Publication Date: 2003-Mar-10
Included in the Prior Art Database: 2003-Mar-10
Document File: 6 page(s) / 71K

Publishing Venue

Motorola

Related People

Authors:
Ravindraraj Ramaraju

Abstract

With aggressive scaling of power supply for higher performance and reduced power dissipation, the sensitivity to the variation in the power supply is greatly increased and robustness of the power grid is essential. More metal layers are needed to route due to increased complexity of the microprocessor and the growing conflict between efficient use of metal for power grid and routing channels. This publication explores designing the power grid in a novel approach to minimize the usage of metal in a layer and have the same robustness of an uniform grid structure by progressively tapering the metal lines away from the contact point, known as a C4 contact point, for a microprocessor design with uniform current distribution.