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Method and apparatus to arbitrate results from several execution units with different latencies in a micropocessor system Disclosure Number: IPCOM000011910D
Original Publication Date: 2003-Mar-25
Included in the Prior Art Database: 2003-Mar-25

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In a microprocessor, an issue queue can issue one instruction per cycle to one of the three execution units. However, due to different in execution latency between the type of instructions in the execution units, two or more instructions can produce the results in the same cycle. In order to reduce the number of write ports to the Register File, the three execution units can share a single result bus. To prevent result data collision between the three execution units, a result bus arbitration scheme is required.