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Method and mechanism to tie sampled performance monitor event
with a specific latency
English (United States)
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Method and mechanism to tie sampled performance monitor event with a specific latency
The mechanism ties the collection the instruction address, data address (if appropriate), and the latency for an event within the sampling mechanism. Current hardware performance monitors, have the ability to count events, sample events with addresses such as instruction address and/or data address associated with the event, as well as monitor event latency. The invention modifies sampling so the instruction and data address (if appropriate) are saved, but additional information recording is possible, maybe using a programmable counter, to "save" the latency for the event when it is sampled. This requires that events are time-stamped, so their latency can be recorded.
For example, consider data TLB misses are being sampled. Each TLB miss requires that the start and stop time of the TLB miss is captured. Also captured are the address of the instruction causing the miss and the data address of the miss. The start time is subtracted from the end time to get a latency, which is saved in a counter. Software extracts this information and presents it in tools. This mechanism is useful for examining any multi-cycle operation in the microprocessor.
Disclosed by International Business Machines Corporation