Browse Prior Art Database

2-Transistor Flash Memory Cell with Low Operating Voltage and No Read Disturb

IP.com Disclosure Number: IPCOM000012078D
Original Publication Date: 2003-Apr-07
Included in the Prior Art Database: 2003-Apr-07

Publishing Venue

Motorola

Related People

Authors:
Jane Yater Bruce Morton Erwin Prinz Craig Swift

Abstract

SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) is an attractive non-volatile memory technology due to reduced process complexity, lower program and erase voltages, and improved extrinsic reliability compared to floating gate memory. Low voltage operation of Flash EEPROM memory can be obtained by using a thin film storage device, such as SONOS, with a tunnel oxide thickness in the range of 15-30Å. By splitting the bias between the gate and substrate, the voltages required for program/erase operation can be reduced in magnitude to 3-8V. However, read disturb is a concern for thin film memories due to the thin dielectric films used to achieve fast tunnel erase speeds, [1]. Gate voltages of 2-3V can cause unacceptable charge loss for bitcells in the low Vt state. To eliminate read disturb, no additional electric field should be applied that would cause charge to move out of or into the storage medium. This paper describes a 2-transistor source-select flash memory cell operating in depletion mode that eliminates read disturb. Programming to the high Vt state is achieved through hot carrier injection (HCI) or uniform tunnel operation while erase is obtained through uniform tunneling. Either a common or decoded source design is possible.