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Timing Margin Improvement with Dual Vref and Receiver for Source Synchronous or Common Clock Single-Ended Bus

IP.com Disclosure Number: IPCOM000012122D
Publication Date: 2003-Apr-09

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that uses dual reference voltages (Vrefs) to improve the timing margin for a source synchronous or common clock single-ended bus.