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Functional Diagnostics Access for Dense PCB Assemblies Disclosure Number: IPCOM000012169D
Original Publication Date: 2003-Apr-15
Included in the Prior Art Database: 2003-Apr-15
Document File: 2 page(s) / 80K

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This article describes a method for providing non-invasive debug access for surface mount chips on a printed circuit board. The method requires a minimum of dedicated real-estate on the unit under test, and can allow access to 100% of the pins on a chip.

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Functional Diagnostics Access for Dense PCB Assemblies

As PCBs get denser, it becomes increasingly hard to find room to provide debug access. This is exacerbated by the increasing width, speed and number of busses on a PCB. If adequate debug access cannot be provided, then product development cycles can be lengthened by an inability to quickly diagnose problems. The solution described is able to make use of the existing via pattern found underneath a BGA site to provide non-invasive functional test access. Test access is mainly provided to the signals at the BGA, but nearby signals can also be picked up using adjacent surface pads. The test connection leads to minimal electrical disturbance of the signals under test. The methodology places a very few demands on the layout of the PCB, and no demands on the routing of traces (no test stubs needed). The solution is robust and reliable enough for standard development lab debug applications. The solution is cheap to produce, as no dedicated test connectors are required on the target PCB.

    Modern high-I/O count chips are typically packaged in Ball-Grid Array packaging: this is a surface mount package with a regular array of solder balls which can be soldered to a PCB. For each ball, there is typically an associated via through the PCB to allow the signal from the ball to be routed through the internal layers of the board. This gives as a side-effect an array of vias on the underside of the PCB: one for each I/O. Normally, these vias are covered with a solder-resist so that there is no electrical connection possible on the underside of the card. For our solution, the vias are left exposed (and for longevity of use, can be finished with a thin flash of gold). This now gives a good electrical contact point to each signal going to or from the BGA (note that the via pattern itself requires no modification: however larger pads can be used in order to increase the contact area).

    To pick up on these points, a Test Card is produced which contains an array of contact pads which are the mirror image of the via breakout from the BGA on the underside of the card. This Test Card then tracks the required signals to debug connectors for analysis (via...