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Method for a high-performance bias generator Disclosure Number: IPCOM000012450D
Publication Date: 2003-May-07
Document File: 4 page(s) / 56K

Publishing Venue

The Prior Art Database


Disclosed is a method for a high-performance bias generator. Benefits include improved performance.

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Method for a high-performance bias generator

Disclosed is a method for a high-performance bias generator. Benefits include improved performance.


        � � � � � Bias generators can be burdensome due to their static current and the resulting power dissipation.

        � � � � � For advanced processes that support legacy high-voltage interfaces, slew rate becomes difficult to maintain because of the disproportionately high� threshold voltage of the thick gate devices used to implement high-voltage circuits. The circuit becomes an enabler for the interfaces because bias generators can easily consume enough static current to make a product economically unfeasable.

General description

        � � � � � The disclosed method uses a common gate amplifier to produce a stable voltage, while consuming less static current. This design is limited to the bias of a P-cascade protection device at an output driver. This limit enables a bias generator design that provides good performance in restoring the bias voltage from a high excursion, while neglecting performance on the low excursions. Application to the symmetrically opposite rail may also be achieved.


        � � � � � Some implementations of the disclosed structure and method provide one or more of the following advantages:�

•        � � � � Reduction of� power due to improved static dissipation

•        � � � � Improved performance in maintaining the driver strength at the output

Detailed description

        � � � � � The disclosed method includes a design for a bias generator (see Figure 1).� The upper side of the bias generator is comprised of transistors m2 – m6.� A divider is formed by m2 – m5, delivering a bias voltage of one half of the rail voltage to the gate of m6.� M6 is a body-effected N device so that its gate bias of approximately 1.65v, will result in current through the device whenever its source is 0.8 volts or less.� This part of the bias generator pulls up low excursions, but needs minimal bias current when the bias generator’s output is 0.8 volts.

The bias current for M6 is provided by M7.� M7 is biased in near subthreshold by the output of the common gate amplifier composed of M1, R1 and R2.� This is how a low bias current is achieved in this design.� However, large current on demand is activated by the com...