Browse Prior Art Database

Method for Reducing Read Cycle Time Using Memory Banking Disclosure Number: IPCOM000012572D
Original Publication Date: 2003-May-15
Included in the Prior Art Database: 2003-May-15
Document File: 2 page(s) / 29K

Publishing Venue



This concept improves memory read cycle time. Memory banking is used to reduce read cycle time by N, where N is the number of memory banks. The invention is particularly useful in server or networking table-look-up applications where read cycles are much more frequent than write cycles (> 80%). For example, if the number of memory banks is four, and the memory core cycle time is 8ns, then this invention allows 2ns read cycle times. Write cycle times are not reduced and are kept at the memory core cycle time, thus, making this invention particularly helpful for read-cycle -intensive applications.

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Method for Reducing Read Cycle Time Using Memory Banking

  The performance advantage is achieved by partitioning memory arrays into separate addressable units or banks. This disclosure describes a four-bank approach. Figure 1 shows the invention. During write cycles, all four banks are written at the same time with the same data. A copy of the data appears on all four banks. During read cycles, the banks are read in sequence, starting at any particular bank. Since the same data appears on all four banks for any given entry, the banks may be read sequentially at one-fourth the memory core cycle time. Signal BANKING in Figure 1 enables the fast cycle mode. In banking mode, a two-bit counter is used to control a bank decoder during read cycles. The counter sequences the banks and muxes the data from a particular bank enabled for the given cycle. During write cycles, the bank decoder selects all banks and enables the write to occur to all four banks.

Figure 2 shows a timing diagram of the concept. Each memory operation has a four-cycle latency. Since write operations require all four banks to be written, then the next operation can occur four cycles later. During read cycles, the banks are


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sequenced and back-to-back operations can occur on every cycle. A NOP instruction is inserted between the write cycle and the read cycle. This allows a refresh operation to occur on Bank4. Furthermore, when going f...