METHOD FOR IMPROVING MATCH PERFORMANCE IN NETWORK SRAM
Original Publication Date: 2003-May-15
Included in the Prior Art Database: 2003-May-15
Disclosed is a method for improving access time in a network (QDR) SRAM. Read cycles require an address compare of a read address captured on the rising edge of the clock to a write address captured on the falling edge of the clock. The time that it takes to compare two wide address busses starting mid-cycle is longer than performing an array access from the rising edge of the clock. If the read and write addresses are not the same, then data from the array is output. If read and write addresses are the same, then a match is generated to output data from write buffers rather than the array. The latency of the match operation starting mid-cycle limits the SRAM's cycle time.