Browse Prior Art Database

Original Publication Date: 2003-May-15
Included in the Prior Art Database: 2003-May-15
Document File: 3 page(s) / 24K

Publishing Venue



Disclosed is a method for improving access time in a network (QDR) SRAM. Read cycles require an address compare of a read address captured on the rising edge of the clock to a write address captured on the falling edge of the clock. The time that it takes to compare two wide address busses starting mid-cycle is longer than performing an array access from the rising edge of the clock. If the read and write addresses are not the same, then data from the array is output. If read and write addresses are the same, then a match is generated to output data from write buffers rather than the array. The latency of the match operation starting mid-cycle limits the SRAM's cycle time.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 75% of the total text.

Page 1 of 3


  The concept solves the access liming bottleneck created by the match operation. The match access is improved to be faster than the array access. Therefore, a match access no longer limits the cycle time. The invention assumes that a match is to occur during the read cycle. When the write operation occurs and write addresses are captured, a MIS-match is generated. Since a MIS-match needs only one address to be different, wide-OR structures rather than AND structures can be used to create the MIS-match. Furthermore, dynamic precharge OR circuits (see mis-compare circuit below) can be used to perform this operation with the precharge stage being the match state.

During the mid-cycle write operation, any one address mis-compared is ORed to null the compare condition initiated during the read cycle. A /Y-Match is created to steer data from the array (if mis-compared) or kept asserted if a match remains. The Z-Match operation (read compare with previous write cycle address) is done in parallel using the conventional AND structure, but will not gate access time because it is initiated at the rising edge of the clock (has extra half-cycle to complete), concurrent with the read access. The Mis-compare circuit shows a first stage comprising a dynamic AND structure where write clock Clkwr starts the mis-compare. A second stage comprises a dynamic OR function that combines all addresses. Any one address that mis-compares...