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Dispatch, Issue, Completion Throttling in SMT

IP.com Disclosure Number: IPCOM000012588D
Original Publication Date: 2003-May-16
Included in the Prior Art Database: 2003-May-16

Publishing Venue

IBM

Abstract

In an SMT processor core it is desirable to be able to throttle instruction flow, on a per-thread basis, at multiple points in the pipeline. Disclosed is a method for throttling instructions at Dispatch, Issue, and Completion.