SMT address trickling
Original Publication Date: 2003-May-19
Included in the Prior Art Database: 2003-May-19
In an SMT processor core with a shared instruction decode/dispatch pipeline, a means is required for a thread with an exception to obtain its next instruction address (NIA), even if the pipeline is blocked by another thread. Disclosed is a method for obtaining that address, utilizing Dispatch Flushes and cache line buffer (CLB) holds. Also disclosed is an alternate mode of operation to allow for more conservative handling of this function, without the dispatch flush requirement. Further, a dispatch fairness mode is disclosed to ensure forward progress is made by any thread, in the presence of dispatch flushes for exception handling.