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Fast isync completion for SMT

IP.com Disclosure Number: IPCOM000012664D
Original Publication Date: 2003-May-19
Included in the Prior Art Database: 2003-May-19

Publishing Venue

IBM

Abstract

In an SMT processor core with shared exception handling logic, overhead is introduced whenever an instruction has an exception or if the instruction is in a category that requires special processing at completion time (a.k.a. "ugly-ops"). Although exceptions and ugly-ops are generally rare, a particular ugly-op, isync, can be fairly frequent, and the overhead of a thread's arbitration and use of the exception handling logic is undesirable. A method is disclosed for more efficient isync processing in an SMT processor core with shared exception handling logic.