Engineered Wires design database
Original Publication Date: 2003-May-20
Included in the Prior Art Database: 2003-May-20
This disclosure describe a design methodology for managing enginnered wires on a System on a Chip (SOC) designs. Due to the large distances that signals need to travel, wire delay is becoming more and more critital to meeting frequency targets. Therefore these wires need to be design and carefully specified. This is a tedious and error prone work and it needs a methodoly such as this invention to manage the design.