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Digital Sample Decimator Disclosure Number: IPCOM000012734D
Original Publication Date: 2003-May-23
Included in the Prior Art Database: 2003-May-23

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Disclosed is a method to reduce the size and power dissipation of digital sample decimator (DSD) in case the internal low pass filter (LPF) is implemented with finite impulse response (FIR) digital filter in which distributed arithmetic algorithm is applied. This method reduces the size of look up table (LUT) and power dissipation in operation by applying special features of DSD.

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Digital Sample Decimator

   Disclosed is a method to reduce the size and power dissipation of digital sample decimator (DSD) in case the internal low pass filter (LPF) is implemented with finite impulse response (FIR) digital filter in which distributed arithmetic algorithm is applied. This method reduces the size of look up table (LUT) and power dissipation in operation by applying special features of DSD. 

Figure 1 shows the structure of DSD with the decimation ratio of "L". The input data "X" with the frequency of "f" is converted to the output data "Y" with the frequency of "f/L". In order to remove aliasing component, filter operation by LPF is required before down sampling. 

The LPF in the DSD is implemented with FIR filter in which distributed arithmetic algorithm is applied. Figure 2 shows the detailed structure of DSD. The effect of the proposed method is to save the size and the power dissipation by the following means:

(1) removing the sample calculation for timing of "nL + i" (where n = 0, 1, 2, ...; i = 1, 2, ..., L-1)     (performing the sample     calculation only for the timing of "nL + i" (where n = 0, 1, 2, ...; i = 0),     that is, "nL",  
(2) segmenting the LUT by grouping the LUT access with the number "i" (i = 0, 1, 2, ..., L-1) and
(3) halving the LUT and accessing twice by making use of symmetrical character of the FIR filter     coefficient.

Means (1) is implemented in the following way. In the Figure 2, address generator uses decimated clock with the frequency of "f/L" which is conventionally input data clock with the frequency of "f". Figure 3 shows the structure of the address generator.  The LUT access is performed only with "f/L" clock cycle which is enough for the DSD with the ratio of "L". This reduces the numbers of the LUT access down to "1/f" of conventional LUT access. Means (2) is explained with the Figure 4. The LUT access is classified into "L" groups and LUT is segmented into "L" pieces. Figure 5 shows the content of each segmented LUTs. The address converter converts external LUT addresses into internal ones for the segmented LUTs by just arranging their orders. With this segmentation, the address size of the LUT size is reduced from "2(mL + 1...