Digital Sample Decimator
Original Publication Date: 2003-May-23
Included in the Prior Art Database: 2003-May-23
Disclosed is a method to reduce the size and power dissipation of digital sample decimator (DSD) in case the internal low pass filter (LPF) is implemented with finite impulse response (FIR) digital filter in which distributed arithmetic algorithm is applied. This method reduces the size of look up table (LUT) and power dissipation in operation by applying special features of DSD.