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Simultaneous Multithreading (SMT) Independent Status Bit Usage

IP.com Disclosure Number: IPCOM000012755D
Original Publication Date: 2003-May-27
Included in the Prior Art Database: 2003-May-27

Publishing Venue

IBM

Abstract

In SMT mode, the register renaming logic must support the status of the physical registers for each thread simultaneously. The status bits that indicate which physical registers are being used by either thread are contained in single vector. When one thread is allocating new registers, the other thread could be freeing up registers via a flush or completion operation