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Customizable Network Translation Protocol Using Embedded FPGAs Disclosure Number: IPCOM000012809D
Original Publication Date: 2003-May-29
Included in the Prior Art Database: 2003-May-29
Document File: 3 page(s) / 13K

Publishing Venue



This invention describes the use of one or more FGPA blocks within a System On A Chip (SOC) to translate between different networking protocols. The fixed portions of the SOC such as a processor and memory controller then may be optimized for size, power, etc. This approach allows a single chip part number to be used in a variety of applications which require protocol translation. This is more cost effective than creating multiple part numbers to cover the same number of applications. It provides support for existing protocols such as Fibre Channel, Ethernet (iSCSI, FCIP, etc.), and InfiniBand, as well as for new formats which may not be known when the chip is designed.

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Customizable Network Translation Protocol Using Embedded FPGAs

      In a mixed network protocol environment, a significant amount of CPU horse power can be consumed moving and/or translating the information from one protocol to another. This is exacerbated in a storage environment because of the desire for the lowest possible latency to enhance system performance. There is also a desire to minimize the number of chip part numbers for handling protocol conversion. This can be solved by a chip which can be easily customized for protocol conversion task.

Background of Invention:

The ability to place Field Programmable Gate Array (FPGA) logic onto an ASIC chip has now been achieved. This combination of standard cell logic with programmable logic will enable many useful functions, one of which is described in this invention. This invention takes advantage of one or more of the following unique benefits gained from a mix of the two technologies:

1. Best of Both Technologies: ASIC hard and soft cores, including mixed signal cores, may be shared with FPGA cells on the same die.

2. Customization: An ASIC containing a field programmable logic core allows each customer to customize the function of the part to serve their own value added applications.

3. Efficient Use of Silicon and I/O's: The ASIC can support a large library of functions which the customer can swap in and out as needed without the need to implement all of the functions in silicon at once.

4. Fast Time To Market: The ASIC can be developed with less turns, supporting faster time to market for the supplier, since logic areas considered high risk may be implemented in programmable cells.

5. Reliability: The FPGA block provides it's own logic configuration interface, separate and independent from the configuration space for the standard cell logic.

6. IP Protection: Valuable hard IP blocks can be protected from reverse engineering at the silicon level by implementing a portion of the IP block in FPGA gates which are personalized aft...