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Customizable Network Translation Protocol Using Embedded FPGAs

IP.com Disclosure Number: IPCOM000012809D
Original Publication Date: 2003-May-29
Included in the Prior Art Database: 2003-May-29

Publishing Venue

IBM

Abstract

This invention describes the use of one or more FGPA blocks within a System On A Chip (SOC) to translate between different networking protocols. The fixed portions of the SOC such as a processor and memory controller then may be optimized for size, power, etc. This approach allows a single chip part number to be used in a variety of applications which require protocol translation. This is more cost effective than creating multiple part numbers to cover the same number of applications. It provides support for existing protocols such as Fibre Channel, Ethernet (iSCSI, FCIP, etc.), and InfiniBand, as well as for new formats which may not be known when the chip is designed.