A process for detecting performance design problems during random functional verification
Original Publication Date: 2003-Jun-04
Included in the Prior Art Database: 2003-Jun-04
Traditionally, performance verification of logic systems has been a difficult manual process. It frequently fails to detect logic errors which can cause significant performance loss. This paper presents a process for detecting most of these logic errors during the random functional verification. It consists of capturing the times of logic signals that represent the start end of performance critical functions. The duration of these functions are then displayed in histograms that represent a distribution of the function time under various conditions. A performance related logic design error appears as anomaly in a histogram.