Method and System for System on Chip Framework Verification
Publication Date: 2003-Jun-05
The IP.com Prior Art Database
A method and system for testing and verifying the framework of a system on chip design is provided. Behavioral models are associated with a device under test which is representative of an integrated circuit. The behavioral models are able to be utilized in a repeated fashion to test components of the device under test when implemented in combination to verify the operation of the device under test without having to rewrite behavioral constructs upon subsequent testing.