Browse Prior Art Database

METHOD FOR IMPLEMENTING PRECISE EXCEPTIONS

IP.com Disclosure Number: IPCOM000013024D
Original Publication Date: 2000-Mar-01
Included in the Prior Art Database: 2003-Jun-12

Publishing Venue

IBM

Abstract

Precise exceptions are an important part of the specification in many architectures. (This is true for both real architectures and virtual machines such as the Java Virtual Machine) The present invention describes how to achieve correct implementation of such architectures during binary translation when speculation and instruction scheduling are to be used to achieve high perform- ance. The present invention describes a code generation technique and runtime environment to be used for implementing precise exceptions while preserving scheduling freedom. The present invention has multiple applications, such as in the binary trans- lation of CISC architectures or in scheduling of unsafe oper- ations. BINARY TRANSLATION OF CISC ARCHITECTURES When using system-level binary translation in CISC architectures, correct exception and trap points must be recognized at the CISC instruction boundary even when a CISC instruction has been cracked into multiple execution primitives. When using an incre- mental commit strategy, atomic instruction execution can be achieved by establishing whether an instruction will succeed before actually modifying any architected processor state.