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Method and Apparatus to prevent output noise in Nor Complex Dynamic Circuits Disclosure Number: IPCOM000013224D
Original Publication Date: 1999-Nov-01
Included in the Prior Art Database: 2003-Jun-18

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Daniel Stasiak Andy Davies


There are output noise problems when designing complex dynamic circuits with static NOR logic. Fig. 1 shows an example of a 4-way AND dynamic circuit using a static NOR in the final stage. One problem with complex NOR dynamic circuits is charge sharing between INT_OUT and the output ABCD. The transistor NDIS discharges INT_OUT during precharge and prevents charge sharing from occurring. Another output noise problem occurs when PRE drops to gnd and PRE1 partially drops unintentionally due to circuit input noise. When PRE falls, the NOR circuit becomes an inverter to PRE1 with a 45u pfet, PNOR2, and 4u nfet, NNOR2. The beta ratio of 45u/6u=7.5 is heavily skewed and allows noise from PRE1 through to the output ABCD. Transistors NNOR3 and NNOR4 will balance this beta ratio of the NOR circuit to prevent noise propagation. NNOR3 is gated by an external signal, DVS_MODE, which controls when to implement this invention, such as during Test, Burn-in or dynamic voltage swing (DVS) mode. The same problem occurs when PRE1 falls and PRE has a low noise pulse, but NDIS solves this problem by balancing the beta ratio for PNOR1 and NNOR1 in a similar fashion as NNOR3 and NNOR4 in the previous case. Fig. 2 is another implementation of the invention that reduces loading on PRE1. Feedback from the circuit output, ABCD, is inverted and sent to NNOR4. During precharge PRE and PRE1 are high, ABCD is low and FBACK2 is high turning NNOR4 on. When NNOR4 and NNOR3 are on, the output, ABCD is held low during the noise event described earlier. :artwork depth='8i' label='Fig. 1'. :artwork depth='7i' label='Fig. 2'. 1