Hybrid Transitional Coding of Wide On-Chip Busses
Original Publication Date: 2001-Nov-10
Included in the Prior Art Database: 2003-Jun-18
On-Chip bus architectures are tending to use ever wider address and data paths, for example, bus data path widths of 128 bits are now relatively common, and some scaleable architectures allow widths of as much as 1024 bits. Implementing such structures can lead to significant on-chip circuit problems. The simultaneous switching of large numbers of driver circuits can cause ground and power grid voltage shifts due to the large transient current demand, driver power dissipation becomes a concern, and routing a bus with such large numbers of connections becomes difficult, especially if it connects to multiple locations, or must extend over a significant distance. CMOS bus data driver circuits are somewhat resistive, and the bus wirng itself tends to have an appreciable amount of destributed resistance and capacitance, so often large driver devices must be used, with signal buffering at different locations to ensure sufficient signal integrity. Proper clocking of such buffers must be ensured, and often a significant amount of chip develoment and design time is devoted to solving timing closure and related problems, so that these data paths can be relied upon to propagate all possible data patterns without error. Transitional Coding techniques can be used to replace these large data busses with ultra high speed asynchronous connections, involving much fewer signals with periodic repowering along the data transmission path. The original large parallel data bus signals would be reconstructed at the destination points, allowing logic design of existing bus components/cores to be unchanged, and thereby leveraging the significant investment in bus architecture and component core designs intended to attach to such bus structures. Only the data transmission paths are replaced, using an encode logic block at the source of the bus, repowering blocks at regular intervals along the path, and a decode logic block at the destination. All other signalling and bus architecture would not change. This adds a small amount of additional logic, but preserves existing IP investment and provides a growth path to cores intended to connect to much wider data bus widths. As one example, the well defined CoreConnect bus standard is expected to benefit in particular from the use of such techniques. Transitional Coding (Patent Pending) uses the change of state (in either direction) of a single line from among a group of lines to signal information. The amount of information transferred by one such transition depends on the size of the group. A group of 4 wires is considered optimal, and each single transition then sends 2 bits of information, as there are 4 possibilities as to which one of the 4 wires is transitioned. This form of encoding is self-clocking and fast, as the data can be decoded as soon as receiving logic detects any incoming line changing state. Synchronous data transmission is possible, in which the sending logic launches transitions at a fixed rate, such that they are always guaranteed to arrive in order at the receiver. An asynchronous interlocked mode of operation is also possible, in which a transmitter only launches the next data transition after it has received an interlock transition back from the receiver. No clocking or timing verification is required in this case, and the circuitry always operates as fast as possible for that specific implementation.